1. Field of the Invention
The present invention relates to ferroelectric memory devices and, more particularly, to structures of memory cell capacitors in the ferroelectric memory devices.
2. Description of the Related Art
A ferroelectric memory has a memory cell structure that is composed of a ferroelectric capacitor (herein after, also referred to as a memory cell capacitor) which holds a polarity of an applied voltage as data, and an access transistor (herein after, also referred to as a memory cell transistor) which executes data access to the memory cell capacitor. As a method of processing this memory cell structure, Japanese Published Patent Application No. 2002-198494 discloses a method by which an upper electrode of the memory cell capacitor and a ferroelectric layer thereof are processed using the same mask, as an example.
FIG. 25(a) is a diagram for explaining a conventional ferroelectric memory device, and shows a layout of electrodes of ferroelectric capacitors which constitute memory cells. FIG. 25(b) is a cross-sectional view along the line XXVa-XXVa of FIG. 25(a), and illustrates a cross-sectional structure of the ferroelectric capacitor.
The conventional ferroelectric memory device 100 has plural memory cells each composed of a memory cell capacitor 100a and a memory cell transistor (not shown). The ferroelectric capacitor 100a is composed of a lower electrode 12 formed on the substrate (not shown), a ferroelectric layer 13 formed on the lower electrode 12, and an upper electrode formed on the ferroelectric layer 13.
The lower electrodes 12 of the respective memory cell capacitors are independent of the respective memory cell capacitors. The lower electrodes 12 of the respective memory capacitors are arranged in a matrix on a memory cell array (not shown) of the ferroelectric memory device 100 along a first direction (herein after, also referred to as “a horizontal direction”) D1 and a second direction (herein after, also referred to as “a vertical direction”) D2.
The ferroelectric layer 13 is common to a certain number of memory cells which are arranged along the vertical direction D2, and it extends in the vertical direction D2 across the plural lower electrodes 12 which are arranged along the vertical direction D2.
The upper electrode 14 is common to a certain number of memory cells which are arranged along the vertical direction D2, like the ferroelectric layer 13. This upper electrode extends in the vertical direction D2 across the plural lower electrodes 12 which are arranged along the vertical direction D2, and it constitutes a plate electrode corresponding to each of the lower electrode arrays along the vertical direction D2.
Next, the step of processing the memory cell structure will be briefly described.
Initially, after an insulating film (not shown) is formed on a semiconductor substrate (not shown) on which memory cell transistors are formed, a contact 1 is formed in the insulating film, and then a lower electrode layer is formed on the entire surface. Then, the lower electrode layer is processed so as to be separated into lower electrodes 12 of the respective memory cell capacitors. Thereafter, a ferroelectric layer and an upper electrode layer are successively formed thereon, and these layers are processed using the same mask, thereby forming plate electrodes each comprising the ferroelectric layer 13 and the upper electrode 14.
In this conventional memory cell structure processing method, since the upper electrode and the ferroelectric layer are processed using the same mask, it is required that the upper electrode 14 should be processed to have a larger width than that of the lower electrode 12, as shown in FIG. 25(a), so as not to cause current leakage between the upper electrode and the lower electrode. This also becomes an obstruction to reduction of the memory cell.
That is, as the upper electrodes 14 are each disposed on an uneven ground plane due to the thickness of the lower electrode 12, the minimum placement interval of the upper electrodes 14 needs to be larger than the minimum placement interval of the lower electrodes 12 which are placed on an even ground plane, depending on conditions in processing the upper electrodes 14. In such cases, the interval of memory cell capacitors, i.e., the interval d12 between areas at which the upper electrode 14 and the lower electrode 12 are overlapped with each other has a dimension that is obtained by summing the minimum placement interval d14 of the upper electrodes and the distance 2·Δd by which the right or left edge of the upper electrode protrude from the right or left edge of the lower electrode. This placement interval d12 (=d14+2·Δd) would be quite larger than the minimum placement interval of the lower electrodes 12.
Further, the structure of the memory cell capacitor is not limited to the above-mentioned planar type structure that is formed by successively laminating a lower electrode, a ferroelectric layer, and an upper electrode on a substrate, but the memory cell capacitor may have a three-dimensional type structure, i.e., a three-dimensional structure that is formed by laminating a lower electrode, a ferroelectric layer, and an upper electrode in a recessed portion having a rectangular opening that is formed in an insulating layer.
FIG. 26(a) is a diagram for explaining a conventional ferroelectric memory device in which memory cell capacitors have three-dimensional structures, and shows a layout of electrodes of ferroelectric capacitors that constitute memory cells. FIG. 26(b) and FIG. 26(c) are a cross-sectional view along the line XXVIa-XXVIa and a cross-sectional view along the line XXVIb-XXVIb of FIG. 26(a), respectively, and show cross-sectional structures of the ferroelectric capacitors.
This ferroelectric memory device 200 has plural memory cells each composed of a memory cell capacitor 200a having a three-dimensional structure and a memory cell transistor (not shown).
The memory cell capacitor 200a of such three-dimensional structure is produced by creating a through hole having a rectangular opening and reaching the lower electrode in an inter layer insulating film on the lower electrode, and successively forming a base electrode layer, a ferroelectric layer, and an upper electrode layer on the inter layer insulating film in such a manner that these layers are laminated on inner walls of the through hole and limb portions of the through hole opening.
That is, the memory cell capacitor 200a of three-dimensional structure is composed of a lower electrode 22 formed on a substrate (not shown), a base electrode layer 25 formed in a through hole of an inter layer insulating film (not shown) and on limb portions on the lower electrode 22, a ferroelectric layer 23 formed on the base electrode layer 25, and an upper electrode 24 formed on the ferroelectric layer 23. In this figure, reference numeral 200b denotes a recessed portion that is formed on the surface of the memory cell capacitor 200a having the three-dimensional structure.
In the case of the memory cell capacitor having such a three-dimensional structure, however, when the size of the through hole opening formed on the inter layer insulating film is reduced to reduce the memory cell size, it becomes difficult to thinly produce the electrode layers or the ferroelectric layer on the through hole inner walls by the typical film formation process such as sputtering or vapor deposition, and consequently, the capacitance of the memory cell capacitor has become unfavorably greatly reduced. This also has become an obstruction to the reduction of the memory cell size.
The present invention is made to solve the above-mentioned problems, and has for its object to provide a ferroelectric memory device that can reduce the placement interval of the memory cell capacitors and realize a reduced memory size, without occurring current leakages between the upper electrode and the lower electrode in a memory cell capacitor having a planer structure, or characteristics deterioration in a the memory cell capacitor having a three-dimensional structure.